Semiconductor wafers are commonly used in the production of integrated circuit (IC) chips on which circuitry is printed. The circuitry is first printed in miniaturized form onto surfaces of the wafers, then the wafers are broken into circuit chips. But this smaller circuitry requires that wafer surfaces be extremely flat and parallel to ensure that the circuitry can be properly printed over the entire surface of the wafer. To accomplish this, a grinding process is commonly used to improve certain features of the wafers (e.g., flatness and parallelism) after they are cut from an ingot.
Simultaneous double side grinding operates on both sides of the wafer at the same time and produces wafers with highly planarized surfaces. It is therefore a desirable grinding process. Double side grinders that can be used to accomplish this include those manufactured by Koyo Machine Industries Co., Ltd. These grinders use a wafer-clamping device to hold the semiconductor wafer during grinding. The clamping device typically comprises a pair of hydrostatic pads and a pair of grinding wheels. The pads and wheels are oriented in opposed relation to hold the wafer therebetween in a vertical orientation. The hydrostatic pads beneficially produce a fluid barrier between the respective pad and wafer surface for holding the wafer without the rigid pads physically contacting the wafer during grinding. This reduces damage to the wafer that may be caused by physical clamping and allows the wafer to move (rotate) tangentially relative to the pad surfaces with less friction. While this grinding process significantly improves flatness and parallelism of the ground wafer surfaces, it can also cause degradation of the topology and nanotopology (NT) of the wafer surfaces.
Poor nanotopology leads to non-uniform oxide layer removal in a later polishing (CMP) process. This can lead to substantial yield losses for the wafer users such as IC manufacturers. As the IC manufacturers move towards 22 nanometer process technology, the tolerances for nanotopology are projected to become tighter.
In order to identify and address the topology degradation concerns, device and semiconductor material manufacturers consider the nanotopology of the wafer surfaces. Nanotopology has been defined as the deviation of a wafer surface within a spatial wavelength of about 0.2 mm to about 20 mm. This spatial wavelength corresponds very closely to surface features on the nanometer scale for processed semiconductor wafers. The foregoing definition has been proposed by Semiconductor Equipment and Materials International (SEMI), a global trade association for the semiconductor industry (SEMI document 3089). Nanotopology measures the elevational deviations of one surface of the wafer and does not consider thickness variations of the wafer, as with traditional flatness measurements. Several metrology methods have been developed to detect and record these kinds of surface variations. For instance, the measurement deviation of reflected light from incident light allows detection of very small surface variations. These methods are used to measure peak to valley (PV) variations within the wavelength.
Double sided grinding is one process which governs the nanotopology (NT) of finished wafers. NT defects like C-Marks (PV value generally within a radius of 0 to 50 mm of center) and B-Rings (PV value generally within a radius of 100 to 150 mm of center) take form during grinding process and may lead to substantial yield losses. These are two defects which lead to substantial yield losses due to NT. A third defect which leads to losses due to NT is the entrance mark produced on the wafer during wiresaw slicing. Double sided grinding can potentially reduce the entrance mark if the grinding wheels are favorably oriented with respect to the wafer. In the current practice, warp and TTV of the wafer are measured immediately after grinding using a capacitance tool like Kobelco SBW 330, then the wafer is etched and is measured using a laser based tool such as Wafercom. After this, the wafer undergoes various downstream processes like edge polishing, double sided polishing, and final polishing as well as measurements for flatness and edge defects before the NT is checked by a nanomapper.
The current methods of controlling NT try to solve the problem by making adjustments to the grinder, but these solutions do not satisfactorily address the causes of NT degradation. At least one cause of NT degradation is thought to be the clamping state dictated by the interaction between the hydrostatic profile of the pads and the incoming wafer.
After a wafer is loaded into the grinder, it is clamped by the hydrostatic pressure generated by the pads on opposite sides of the wafer. The wafer may be elastically deformed in an initial clamping state based on the interaction between the shape of the incoming wafer and the hydrostatic pressure profile of the hydrostatic pads. After the wheel starts contacting the wafer, there is a period of time where the wheel attempts to grip the wafer without removing a significant amount of material. During this period of time the wafer undergoes further elastic deformation depending on the interaction between tilts and shifts of the wheel and the initial clamping state. The wheels begin grinding the wafer and material is removed from the wafer once a stable state is reached. As the material is being removed in the stable state the NT of the wafer is thought to be a function of the geometric interaction between the wheel and the stable state of the wafer.
After a set amount of material has been removed, the wheels retract and the elastic deformation of the wafer is reversed. The reversal of the elastic deformation after retractions of the wheels further degrades NT. The combined effects of the two contributors to NT degradation—geometric interaction between the wheel and the stable state of the wafer and reversal of the elastic deformation—are difficult to control. Previous approaches have yielded unsatisfactory results in controlling the NT degradation resultant from the elastic deformation of the wafer.
A typical wafer-clamping device 1′ of a double side grinder of the prior art is schematically shown in FIGS. 1 and 2. Grinding wheels 9′ and hydrostatic pads 11′ hold the wafer W independently of one another. They respectively define clamping planes 71′ and 73′. A clamping pressure of the grinding wheels 9′ on the wafer W is centered at a rotational axis 67′ of the wheels, while a clamping pressure of the hydrostatic pads 11′ on the wafer is centered near a center WC of the wafer. As long as clamping planes 71′ and 73′ are held coincident during grinding (FIG. 1), the wafer remains in plane (i.e., does not bend) and is uniformly ground by wheels 9′. A general discussion regarding alignment of clamping planes may be found in U.S. Pat. No. 6,652,358. However, if the two planes 71′ and 73′ become misaligned, the clamping pressures of the grinding wheels 9′ and hydrostatic pads 11′ produce a bending moment, or hydrostatic clamping moment, in the wafer W that causes the wafer to bend sharply generally adjacent peripheral edges 41′ of the grinding wheel openings 39′ (FIG. 2). This produces regions of high localized stress in the wafer W.
Misalignment of clamping planes 71′ and 73′ is common during double side grinding operation and is generally caused by movement of the grinding wheels 9′ relative to the hydrostatic pads 11′ (FIG. 2). Possible modes of misalignment are schematically illustrated in FIGS. 2 and 3. These include a combination of three distinct modes. In the first mode there is a lateral shift S of the grinding wheels 9′ relative to the hydrostatic pads 11′ in translation along an axis of rotation 67′ of the grinding wheels (FIG. 2). A second mode is characterized by a vertical tilt VT of the wheels 9′ about a horizontal axis X through the center of the respective grinding wheel (FIGS. 2 and 3). FIG. 2 illustrates a combination of the first mode and second mode. In a third mode there is a horizontal tilt HT of the wheels 9′ about a vertical axis Y through the center of the respective grinding wheel (FIG. 3). These modes are greatly exaggerated in the drawings to illustrate the concept; actual misalignment may be relatively small. In addition, each of the wheels 9′ is capable of moving independently of the other so that horizontal tilt HT of the left wheel can be different from that of the right wheel, and the same is true for the vertical tilts VT of the two wheels.
The magnitude of hydrostatic clamping moments caused by misalignment of clamping planes 71′ and 73′ is related to the design of the hydrostatic pads 11′. For example, higher moments are generally caused by pads 11′ that clamp a larger area of the wafer W (e.g., pads that have a large working surface area), by pads in which a center of pad clamping is located a relatively large distance apart from the grinding wheel rotational axis 67′, by pads that exert a high hydrostatic pad clamping force on the wafer (i.e., hold the wafer very rigidly), or by pads that exhibit a combination of these features.
In clamping device 1′ using prior art pads 11′ (an example of one prior art pad is shown in FIG. 4), the bending moment in wafer W is relatively large when clamping planes 71′ and 73′ misalign because the wafer is clamped very tightly and rigidly by the pads 11′, including near peripheral edges 41′ of grinding wheel opening 39′. The wafer cannot adjust to movement of grinding wheels 9′ and the wafer bends sharply near opening edges 41′ (FIG. 2). The wafers W are not uniformly ground and they develop undesirable nanotopology features that cannot be removed by subsequent processing (e.g., polishing). Misalignment of clamping planes 71′ and 73′ can also cause the grinding wheels 9′ to wear unevenly, which can further contribute to development of undesirable nanotopology features on the ground wafer W.
FIGS. 5A and 5B illustrate undesirable nanotopology features that can form on surfaces of a ground wafer W when clamping planes 71′ and 73′ misalign and the wafer bends during the grinding operation. The features include center-marks (C-marks) 77′ and B-rings 79′ (FIG. 5A). The center-marks (C-marks) 77′ are generally caused by a combination of lateral shift S and vertical tilt VT of the grinding wheels 9′, while the B-rings 79′ are generally caused by a combination of lateral shift S and horizontal tilt HT of the wheels. As shown in FIG. 5B, both features 77′ and 79′ have relatively large peak to valley variations associated with them. They are therefore indicative of poor wafer nanotopology and can significantly affect ability to print miniaturized circuitry on wafer surfaces.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.